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DATA SHEET
PD780031AY, 780032AY, 780033AY, 780034AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD780031AY, 780032AY, 780033AY, and 780034AY are members of the PD780034AY Subseries of the 78K/0 Series. This is a PD780034A Subseries product with an added multimaster-supporting I2C bus interface, and is suitable for AV equipment applications. A flash memory version, the PD78F0034AY, that can operate in the same power supply voltage range as the mask ROM version, and various development tools, are available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD780024A, 780034A, 780024AY, 780034AY
Subseries User's Manual: 78K/0 Series User's Manual Instructions: U14046E U12326E
FEATURES
* Internal ROM and RAM
Item Part Number Program Memory (Internal ROM) 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 1024 bytes Data Memory (Internal High-Speed RAM) 512 bytes Package
PD780031AY PD780032AY PD780033AY PD780034AY
* 64-pin plastic shrink DIP (750 mils) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm)
* External memory expansion space: 64 Kbytes * Minimum instruction execution time: 0.24 s (@ fX = 8.38-MHz operation) * I/O ports: 51 (5-V-tolerant N-ch open-drain: 4) * 10-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V) * Serial interface: 3 channels (multimaster-supporting I2C bus mode, UART mode, 3-wire serial I/O mode) * Timer: 5 channels * Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Telephones, home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14045EJ1V0DS00 (1st edition) Date Published August 1999 N CP(K) Printed in Japan
(c)
1999
PD780031AY, 780032AY, 780033AY, 780034AY
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic LQFP (12 x 12 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic LQFP (12 x 12 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic LQFP (12 x 12 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic LQFP (12 x 12 mm)
PD780031AYCW-xxx PD780031AYGC-xxx-AB8 PD780031AYGK-xxx-8A8 PD780032AYCW-xxx PD780032AYGC-xxx-AB8 PD780032AYGK-xxx-8A8 PD780033AYCW-xxx PD780033AYGC-xxx-AB8 PD780033AYGK-xxx-8A8 PD780034AYCW-xxx PD780034AYGC-xxx-AB8 PD780034AYGK-xxx-8A8
Remark xxx indicates ROM code suffix.
2
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H
PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y PD780078Y PD780034AY
PD780024AY PD78018FY
PD78054 with added timer and enhanced external interface
ROM-less version of the PD78078 PD78078Y with enhanced serial I/O and limited functions
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with added UART and D/A converter and enhanced I/O PD780024A with increased RAM capacity
A PD780034A with added timer and enhanced serial I/O
PD780024A with enhanced A/D converter PD78018F with enhanced serial I/O EMI-noise reduced version of the PD78018F
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
FIPTM drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 78K/0 Series 100-pin 80-pin 80-pin 80-pin
PD780208 PD780228 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and FIP C/D. Display output total: 53 PD78044H with enhanced I/O and FIP C/D. Display output total: 48
For panel control. On-chip FIP C/D. Display output total: 53
PD78044F with added N-ch open drain I/O. Display output total: 34
Basic subseries for driving FIP. Display output total: 34
100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
PD780308Y PD78064Y
PD78064 with enhanced SIO, and increased ROM, RAM capacity.
EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART
Call ID supported 80-pin
PD780841
Bus interface supported
On-chip Call ID and simple DTMF. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780948 PD78098B PD780701Y PD780833Y
Meter control
On-chip D-CAN controller PD78054 with IEBusTM controller added. EMI-noise reduced. On-chip D-CAN/IEBus controller On-chip controller compliant with J1850 (Class 2)
100-pin 80-pin 80-pin 80-pin
PD780958 PD780955 PD780973 PD780824
For industrial meter control Ultra low-power consumption. On-chip UART. On-chip automobile meter controller/driver For automobile meter. On-chip D-CAN controller.
Data Sheet U14045EJ1V0DS00
3
PD780031AY, 780032AY, 780033AY, 780034AY
The major functional differences among the Y subseries are shown below.
Function ROM Capacity Subseries Name Control Configuration of Serial Interface 3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch 3-wire with automatic transmit/receive function: 1 ch Time-division 3-wire: 1 ch I2C bus (multimaster supported): 1 ch 3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division UART: 1 ch 3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch 3-wire: UART: 3-wire/UART: I2C bus (multimaster supported): UART: 3-wire: I2C bus (multimaster supported): 1 1 1 1 ch ch ch ch I/O VDD MIN. Value 88 61 88 1.8 V 2.7 V
PD78078Y PD78070AY PD780018AY
48 K to 60 K -- 48 K to 60 K
PD780058Y
24 K to 60 K
68
1.8 V
PD78058FY PD78054Y PD780078Y
48 K to 60 K 16 K to 60 K 48 K to 60 K
69
2.7 V 2.0 V
52
1.8 V
PD780034AY PD780024AY PD78018FY
LCD drive
8 K to 32 K
1 ch 1 ch 1 ch
51
1.8 V
8 K to 60 K
3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 3-wire/2-wire/I2C: 3-wire/time-division UART: 3-wire: 3-wire/2-wire/I2C: 3-wire/UART: 1 ch 1 ch 1 ch 1 ch 1 ch
53
PD780308Y
48 K to 60 K
57
2.0 V
PD78064Y
16 K to 32 K
Remark Functions other than the serial interface are common to the non-Y subseries.
4
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
OVERVIEW OF FUNCTIONS
Part Number Item Internal memory Memory space General-purpose registers Minimum instruction execution time ROM High-speed RAM 8 Kbytes 512 bytes 64 Kbytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle variable function 16 Kbytes 24 Kbytes 1024 bytes 32 Kbytes
PD780031AY
PD780032AY
PD780033AY
PD780034AY
When main system 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38-MHz operation) clock selected When subsystem clock selected 122 s (@ 32.768-kHz operation) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. 51
Instruction set
I/O ports
Total:
* CMOS input: 8 * CMOS I/O: 39 * 5-V-tolerant N-ch open-drain I/O: 4 A/D converter * 10-bit resolution x 8 channels * Low-voltage operation available: AVDD = 1.8 to 5.5 V Serial interface * 3-wire serial I/O mode: * UART mode: * I2C bus mode (multimaster supported): * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 1 channel 1 channel 1 channel channel channels channel channel
Timer
Timer output Clock output
3 (8-bit PWM output capable: 2) * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38-MHz operation with main system clock ) * 32.768 kHz (@ 32.768-kHz operation with subsystem clock) 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38-MHz operation with main system clock) Maskable Non-maskable Software Internal: 13, external: 5 Internal: 1 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 64-pin plastic shrink DIP (750 mils) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm)
Buzzer output Vectored interrupt sources
Power supply voltage Operating ambient temperature Package
Data Sheet U14045EJ1V0DS00
5
PD780031AY, 780032AY, 780033AY, 780034AY
CONTENTS
1. PIN CONFIGURATION (Top View) ..................................................................................................... 7 2. BLOCK DIAGRAM .............................................................................................................................10 3. PIN FUNCTIONS ................................................................................................................................ 11
3.1 3.2 3.3 Port Pins .................................................................................................................................................... 11 Non-Port Pins ............................................................................................................................................ 12 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
4. MEMORY SPACE ...............................................................................................................................16 5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................17
5.1 5.2 5.3 5.4 5.5 5.6 Ports ........................................................................................................................................................... 17 Clock Generator ........................................................................................................................................ 18 Timer/Counter ........................................................................................................................................... 19 Clock Output/Buzzer Output Control Circuit ....................................................................................... 23 A/D Converter ........................................................................................................................................... 24 Serial Interface .......................................................................................................................................... 25
6. INTERRUPT FUNCTION ....................................................................................................................28 7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................31 8. STANDBY FUNCTION .......................................................................................................................31 9. RESET FUNCTION ............................................................................................................................31 10. MASK OPTION ...................................................................................................................................31 11. INSTRUCTION SET ...........................................................................................................................32 12. ELECTRICAL SPECIFICATIONS ......................................................................................................34 13. PACKAGE DRAWINGS .....................................................................................................................57 14. RECOMMENDED SOLDERING CONDITIONS ................................................................................60 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................62 APPENDIX B. RELATED DOCUMENTS ...............................................................................................65
6
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
1. PIN CONFIGURATION (Top View)
* 64-pin plastic shrink DIP (750 mils)
PD780031AYCW-xxx, 780032AYCW-xxx, 780033AYCW-xxx, 780034AYCW-xxx
P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P30 P31 P32/SDA0 P33/SCL0 P34 P35 P36 P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 VDD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P67/ASTB P66/WAIT P65/WR P64/RD P75/BUZ P74/PCL P73/TI51/TO51 P72/TI50/TO50 P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 X1 X2 IC XT1 XT2 RESET AVDD AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When the PD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14045EJ1V0DS00
7
PD780031AY, 780032AY, 780033AY, 780034AY
* 64-pin plastic QFP (14 x 14 mm)
PD780031AYGC-xxx-AB8, 780032AYGC-xxx-AB8, 780033AYGC-xxx-AB8, 780034AYGC-xxx-AB8
* 64-pin plastic LQFP (12 x 12 mm)
PD780031AYGK-xxx-8A8, 780032AYGK-xxx-8A8, 780033AYGK-xxx-8A8, 780034AYGK-xxx-8A8
P73/TI51/TO51 P72/TI50/TO50
P67/ASTB
P66/WAIT
P75/BUZ
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P30 P31 P32/SDA0 P33/SCL0 P34 P35
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P74/PCL
P65/WR
P64/RD
P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 X1 X2 IC XT1 XT2 RESET AVDD AVREF P10/ANI0
10 11 12 13 14 15
16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P20/SI30
P23/RxD0
P24/TxD0
P25/ASCK0
P21/SO30
P22/SCK30
AVSS
VDD1
P36
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When the PD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U14045EJ1V0DS00
P11/ANI1
PD780031AY, 780032AY, 780033AY, 780034AY
A8 to A15: AD0 to AD7: ADTRG: ANI0 to ANI7: ASCK0: ASTB: AVDD: AVREF: AVSS: BUZ: IC: INTP0 to INTP3: P00 to P03: P10 to P17: P20 to P25: P30 to P36: P40 to P47: P50 to P57: P64 to P67: Address Bus Address/Data Bus AD Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock Internally Connected External Interrupt Input Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P75: PCL: RD: RESET: RxD0: SCK30, SCL0: SDA0: SI30: SO30: TO0, TO50, TO51: TxD0: VDD0, VDD1: VSS0, VSS1: WAIT: WR: X1, X2: XT1, XT2: Port 7 Programmable Clock Read Strobe Reset Receive Data Serial Clock Serial Data Serial Input Serial Output Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
TI00, TI01, TI50, TI51: Timer Input
Data Sheet U14045EJ1V0DS00
9
PD780031AY, 780032AY, 780033AY, 780034AY
2. BLOCK DIAGRAM
TI00/TO0/P70 TI01/P71 TI50/TO50/P72 TI51/TO51/P73
16-BIT TIMER/ EVENT COUNTER 8-BIT TIMER/ EVENT COUNTER 50 8-BIT TIMER/ EVENT COUNTER 51 WATCHDOG TIMER WATCH TIMER
PORT 0
P00 to P03
PORT 1
P10 to P17
PORT 2
P20 to P25
PORT 3
P30 to P36
78K/0 CPU CORE
ROM
PORT 4
P40 to P47
SI30/P20 SO30/P21 SCK30/P22 RxD0/P23 TxD0/P24 ASCK0/P25 SDA0/P32 SCL0/P33 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 BUZ/P75 PCL/P74
SERIAL INTERFACE 30
PORT 5
P50 to P57
PORT 6 UART0 PORT 7 RAM I C BUS
2
P64 to P67
P70 to P75
AD0/P40 to AD7/P47 A8/P50 to A15/P57 EXTERNAL ACCESS RD/P64 WR/P65 WAIT/P66 ASTB/P67
A/D CONVERTER
INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL VDD0 VDD1 VSS0 VSS1 IC SYSTEM CONTROL RESET X1 X2 XT1 XT2
Remark The internal ROM and RAM capacities differ depending on the product.
10
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name I/O Function After Reset P00 P01 P02 P03 P10 to P17 Input Port 1 8-bit input-only port P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P35 P36 P40 to P47 I/O Port 4 8-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. The interrupt request flag (KRIF) is set to 1 by falling edge detection. P50 to P57 I/O Port 5 8-bit input/output port LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. P64 P65 P66 P67 I/O Port 6 4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. ASTB Input RD WR WAIT Input A8 to A15 Input AD0 to AD7 An on-chip pull-up resistor can be connected by means of software. I/O Port 3 7-bit input/output port Input/output can be specified in 1-bit units. N-ch open-drain input/output port The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31. LEDs can be driven directly. SCL0 -- SDA0 Input I/O Port 2 6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. RxD0 TxD0 ASCK0 -- Input SI30 SO30 SCK30 Input I/O Port 0 4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. INTP3/ADTRG ANI0 to ANI7 Input Alternate Function INTP0 INTP1 INTP2
Data Sheet U14045EJ1V0DS00
11
PD780031AY, 780032AY, 780033AY, 780034AY
3.1 Port Pins (2/2)
Pin Name I/O Function After Reset P70 P71 P72 P73 P74 P75 I/O Port 7 6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. TI51/TO51 PCL BUZ Input Alternate Function TI00/TO0 TI01 TI50/TO50
3.2 Non-Port Pins (1/2)
Pin Name I/O Function After Reset INTP0 INTP1 INTP2 INTP3 SI30 SO30 SDA0 SCK30 SCL0 RxD0 TxD0 ASCK0 TI00 Input Output Input Input Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface Serial clock input for asynchronous serial interface External count clock input to 16-bit timer (TM0) Capture trigger input to capture register (CR01) of 16-bit timer (TM0) TI01 TI50 TI51 TO0 TO50 TO51 PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB Input Output Output Output I/O Output Output Output Capture trigger input to capture register (CR00) of 16-bit timer (TM0) External count clock input to 8-bit timer (TM50) External count clock input to 8-bit timer (TM51) 16-bit timer (TM0) output 8-bit timer (TM50) output (also used for 8-bit PWM output) 8-bit timer (TM51) output (also used for 8-bit PWM output) Clock output (for trimming of main system clock and subsystem clock) Buzzer output Lower address/data bus for expanding memory externally Higher address bus for expanding memory externally Strobe signal output for reading from external memory Strobe signal output for writing to external memory Wait insertion at external memory access Strobe output that externally latches address information output to ports 4 and 5 to access external memory Input Input Input Input Input Input Input Input Input P71 P72/TO50 P73/TO51 P70/TI00 P72/TI50 P73/TI51 P74 P75 P40 to P47 P50 to P57 P64 P65 P66 P67 Input Input Input Input Input Output I/O I/O Serial interface serial data input Serial interface serial data output Serial interface serial data input/output Serial interface serial clock input/output Input Input Input Input Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input Alternate Function P00 P01 P02 P03/ADTRG P20 P21 P32 P22 P33 P23 P24 P25 P70/TO0
12
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
3.2 Non-Port Pins (2/2)
Pin Name I/O Function After Reset ANI0 to ANI7 ADTRG AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 IC Input Input Input -- -- Input Input -- Input -- -- -- -- -- -- Positive power supply for ports Ground potential of ports Positive power supply (except ports) Ground potential (except ports) Internally connected. Connect directly to VSS0 or VSS1. Connecting crystal resonator for subsystem clock oscillation A/D converter analog input A/D converter trigger signal input A/D converter reference voltage input A/D converter analog power supply. Set potential to that of VDD0 or VDD1. A/D converter ground potential. Set potential to that of VSS0 or VSS1. System reset input Connecting crystal resonator for main system clock oscillation Input Input -- -- -- -- -- -- -- -- -- -- -- -- -- Alternate Function P10 to P17 P03/INTP3 -- -- -- -- -- -- -- -- -- -- -- -- --
Data Sheet U14045EJ1V0DS00
13
PD780031AY, 780032AY, 780033AY, 780034AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits
Pin Name Input/Output Circuit Type 8-C I/O Recommended Connection of Unused Pins
P00/INTP0 to P02/INTP2 P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 P30, P31 P32/SDA0 P33/SCL0 P34 P35 P36 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ RESET XT1 XT2 AVDD AVREF AVSS IC
Input
Independently connect to VSS0 via a resistor.
25 8-C 5-H 8-C
Input I/O
Independently connect to VDD0 or VSS0 via a resistor.
5-H 8-C 13-Q 13-R I/O Independently connect to VDD0 via a resistor.
8-C 5-H 8-C 5-H I/O I/O I/O
Independently connect to VDD0 or VSS0 via a resistor.
Independently connect to VDD0 via a resistor. Independently connect to VDD0 or VSS0 via a resistor.
8-C
5-H
2 16
Input Connect to VDD0. -- Leave open. Connect to VDD0. Connect to VSS0.
--
--
Connect directly to VSS0 or VSS1.
14
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 3-1. Pin Input/Output Circuits
TYPE 2 TYPE 13-R
IN/OUT Data Output disable IN N-ch
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
VDD0
TYPE 16
Pullup enable Data
P-ch VDD0 P-ch IN/OUT
Feedback cut-off P-ch
Output disable Input enable TYPE 8-C
N-ch VSS0 XT1 XT2
TYPE 25 VDD0 P-ch P-ch VDD0 P-ch IN/OUT Comparator
+ -
Pullup enable Data
N-ch VSS0 VREF (threshold voltage) Input enable
IN
Output disable
N-ch VSS0
TYPE 13-Q
Mask option
VDD0
IN/OUT Data Output disable N-ch VSS0
Input enable
Data Sheet U14045EJ1V0DS00
15
PD780031AY, 780032AY, 780033AY, 780034AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the PD780031AY, 780032AY, 780033AY, and 780034AY. Figure 4-1. Memory Map
FFFFH Special function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General-purpose registers 32 x 8 bits
Internal high-speed RAMNote mmmmH mmmmH - 1
Data memory space
nnnnH Reserved 1000H 0FFFH F800H F7FFH CALLF entry area 0800H 07FFH External memory Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0000H Program area
Program memory space nnnnH + 1 nnnnH
Internal ROM
Note
Note
The internal ROM and internal high-speed RAM capacities differ depending on the product (see the following table).
Part Number Last Address of Internal ROM nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Start Address of Internal High-Speed RAM mmmmH FD00H
PD780031AY PD780032AY PD780033AY PD780034AY
16
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports The following 3 types of I/O ports are available. * CMOS input (Port 1): * CMOS input/output (Ports 0, 2 to 7, P34 to P36): * N-ch open-drain input/output (P30 to P33): Total: 8 39 4 51 Table 5-1. Port Functions
Name Port 0 Pin Name P00 to P03 Function I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. Dedicated input port pins. I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. N-ch open-drain I/O port pins. Input/output can be specified in 1-bit units. The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31. LEDs can be driven directly. P34 to P36 I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. The interrupt request flag (KRIF) is set to 1 by falling edge detection. I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. LEDs can be driven directly. Port 6 P64 to P67 I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. I/O port pins. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.
Port 1 Port 2
P10 to P17 P20 to P25
Port 3
P30 to P33
Port 4
P40 to P47
Port 5
P50 to P57
Port 7
P70 to P75
Data Sheet U14045EJ1V0DS00
17
PD780031AY, 780032AY, 780033AY, 780034AY
5.2 Clock Generator A system clock generator is incorporated. The minimum instruction execution time can be changed. * 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38-MHz operation with main system clock) * 122 s (@ 32.768-kHz operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
XT1 XT2
Subsystem clock oscillator
fXT Watch timer, clock output function Prescaler 1
X1 X2
Main system clock oscillator
Prescaler fX fX 2 fX 22 fX 23 fX 24
2 fXT 2
Clock to peripheral hardware
STOP
Selector
Standby control circuit
Wait control circuit
CPU clock (fCPU)
18
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
5.3 Timer/Counter Five timer/counter channels are incorporated. * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: * Watch timer: * Watchdog timer: 2 channels 1 channel 1 channel Table 5-2. Operations of Timer/Event Counters
16-Bit Timer/ Event Counter TM0 Operation mode Interval timer External event counter Function Timer output PPG output PWM output Pulse width measurement Square wave output One-shot pulse output Interrupt source 1 output 1 output -- 2 inputs 1 output 1 output 2 2 outputs -- 2 outputs -- 2 outputs -- 2 -- -- -- -- -- -- 2 -- -- -- -- -- -- 1 1 channel 1 channel 2 channels 2 channels 1 channelNote 1 -- 1 channelNote 2 -- 8-Bit Timer/ Event Counters TM50, TM51 Watch Timer Watchdog Timer
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
Data Sheet U14045EJ1V0DS00
19
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter TM0
Internal bus
Selector
INTTM00
TI01/P71
Noise elimination circuit
Selector
16-bit capture/compare register 00 (CR00) Match
Selector
fX fX/22 fX/26 Noise elimination circuit
16-bit timer counter 0 (TM0) Match
Clear
Output control circuit
TO0/TI00/P70
fX/23
TI00/TO0/P70
Selector
Noise elimination circuit
16-bit capture/compare register 01 (CR01) INTTM01
Internal bus
20
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter TM50
Internal bus
Mask circuit
8-bit compare register 50 (CR50) TI50/TO50/P72 fX fX/22 fX/24 fX/26 fX/28 fX/210 Match Selector 8-bit timer counter OVF 50 (TM50) Clear 3 Selector
Selector
INTTM50
Selector
S Q INV R
TO50/TI50/P72
S R
Invert level
TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50)
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter TM51
Internal bus
Mask circuit
8-bit compare register 51 (CR51) TI51/TO51/P73 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Match
Selector
Selector
INTTM51
8-bit timer counter 51 (TM51)
OVF Clear
Selector
S Q INV R
TO51/TI51/P73
3 Selector
S R
Invert level
TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus
Data Sheet U14045EJ1V0DS00
21
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-5. Watch Timer Block Diagram
Clear
Selector
fX/2
7
fW fW 24
9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29
Selector
5-bit counter Clear
INTWT
fXT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus
Figure 5-6. Watchdog Timer Block Diagram
fX/28
Clock input control circuit RUN
Division circuit
Divided clock selection circuit
Output control circuit
INTWDT RESET
Division mode selection circuit
3 WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization time select register (OSTS)
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
Internal bus
22
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
5.4 Clock Output/Buzzer Output Control Circuit A clock output/buzzer output control circuit (CKU) is incorporated. Clocks with the following frequencies can be output as clock output. * 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@ 8.38-MHz operation with main system clock) * 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Clocks with the following frequencies can be output as buzzer output. * 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@ 8.38-MHz operation with main system clock) Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU
fX
Prescaler 8 4 fX/210 to fX/213 Selector
BUZ/P75
BZOE fX to fX/27 Selector Clock control circuit CLOE
BCS0, BCS1
PCL/P74
fXT
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output select register (CKS) Internal bus
Data Sheet U14045EJ1V0DS00
23
PD780031AY, 780032AY, 780033AY, 780034AY
5.5 A/D Converter An A/D converter consisting of eight 10-bit resolution channels is incorporated. The following two A/D conversion operation start-up methods are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive approximation register (SAR) AVSS Selector Tap selector Sample & hold circuit Voltage comparator AVDD AVREF
ADTRG/INTP3/P03
Edge detection circuit
Control circuit
INTAD
Edge detection circuit
A/D conversion result register 0 (ADCR0) INTP3 Internal bus
24
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
5.6 Serial Interface Three serial interface channels are incorporated. * Serial interface UART0: * Serial interface SIO30: * Serial interface IIC0: (1) Serial interface UART0 The serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer mode. * Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin. The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). * Infrared data transfer mode This mode enables pulse output and pulse reception in data format. This mode can be used for office equipment applications such as personal computers. Figure 5-9. Block Diagram of Serial Interface UART0 1 channel 1 channel 1 channel
Internal bus Asynchronous serial interface mode register 0 (ASIM0) TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0
Receive buffer RXB0 register 0 Asynchronous serial interface status register 0 (ASIS0) Transmit TXS0 shift PE0 FE0 OVE0 register 0
RxD0/P23
RX0
Receive shift register 0
TxD0/P24
Receive control circuit (parity check) Transmit
INTSER0 control INTSR0
circuit (parity addition)
INTST0
Baud rate generator
ASCK0/P25 fX/2 to fX/27
Data Sheet U14045EJ1V0DS00
25
PD780031AY, 780032AY, 780033AY, 780034AY
(2) Serial interface SIO30 The serial interface SIO30 has one mode: 3-wire serial I/O mode. * 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30). Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in 8-bit data in the serial transfer is fixed as MSB. The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, display controllers, etc. that include a clocked serial interface. Figure 5-10. Block Diagram of Serial Interface SIO30
Internal bus 8 SI30/P20 Serial I/O shift register 30 (SIO30)
SO30/P21 SCK30/P22 Serial clock counter Serial clock control circuit Interrupt request signal generator INTCSI30 fX/23 fX/24 fX/25
Selector
26
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
(3) Serial interface IIC0 The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported). * I2C bus mode (multimaster supported) This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and serial data bus line (SDA0). This mode complies with the I2C bus format, and can output "start condition", "data", and "stop condition" during transmission via the serial data bus. This data is automatically detected by hardware during reception. Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial data bus line are required. Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus IIC status register 0 (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0 (IICC0) SDA0/P32 Noise elimination circuit Slave address register 0 (SVA0) Matched signal
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
CLEAR SET SO0 latch D CL00
IIC shift register 0 (IIC0)
N-ch opendrain output
Data hold time correction circuit
Acknowledge detection circuit Wake-up control circuit
Acknowledge detection circuit Start condition detection circuit
SCL0/P33 Noise elimination circuit
Stop condition detection circuit Interrupt request signal generator
Serial clock counter
INTIIC0
Serial clock control circuit N-ch open-drain output fX Prescaler
Serial clock wait control circuit
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock select register 0 (IICCL0)
Internal bus
Data Sheet U14045EJ1V0DS00
27
PD780031AY, 780032AY, 780033AY, 780034AY
6. INTERRUPT FUNCTION
A total of 20 interrupt sources are provided, divided into the following three types. * Non-maskable: 1 * Maskable: * Software: 18 1 Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable Maskable Default PriorityNote 1 -- Name INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH Generation of serial interface UART0 reception error End of serial interface UART0 reception End of serial interface UART0 transmission End of serial interface SIO30 transfer End of serial interface IIC0 transfer Reference time interval signal from watch timer Matching of TM0 and CR00 (when CR00 is specified as a compare register) Detection of TI01 pin valid edge (when CR00 is specified as a capture register) Matching of TM0 and CR01 (when CR01 is specified as a compare register) Detection of TI00 pin valid edge (when CR00 is specified as a capture register) Matching of TM50 and CR50 Matching of TM51 and CR51 End of conversion by A/D converter Watch timer overflow Detection of port 4 falling edge Execution of BRK instruction External -- Internal 000EH (B) Internal/ External Internal Vector Table Address 0004H
Basic Configuration TypeNote 2
(A)
0
INTWDT
(B)
1 2 3 4 5
INTP0 INTP1 INTP2 INTP3 INTSER0
(C)
6 7 8 9 10 11
INTSR0 INTST0 INTCSI30 INTIIC0 INTWTI INTTM00
0010H 0012H 0014H 0016H 001AH 001CH
12
INTTM01
001EH
13 14 15 16 17 Software --
INTTM50 INTTM51 INTAD0 INTWT INTKR BRK
0020H 0022H 0024H 0026H 0028H 003EH (D) (E)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 17 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
28
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt edge enable register (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detection circuit
IF
Priority control circuit
Vector table address generator Standby release signal
Data Sheet U14045EJ1V0DS00
29
PD780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Interrupt request 1 when MEM = 01H
Falling edge detection circuit
IF
Priority control circuit
Vector table address generator Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator
IF: IE: ISP: MK: PR:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
MEM: Memory expansion mode register
30
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM, RAM, and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. * STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. This can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped).
Figure 8-1. Standby Function
CSS = 1 Main system clock operation STOP instruction Interrupt request HALT mode Clock supply for CPU is stopped, oscillation is maintained CSS = 0 HALT instruction Interrupt request HALT mode Clock supply for CPU is stopped, oscillation is maintained Subsystem clock operation HALT instruction
Interrupt request
STOP mode Main system clock operation is stopped
9. RESET FUNCTION
The following two reset methods are available. * External reset by RESET signal input * Internal reset by watchdog timer runaway time detection
10. MASK OPTION
Table 10.1 Pin Mask Option Selection
Pins P30, P31 Mask Option An on-chip pull-up resistor can be specified in 1-bit units.
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31, in 1-bit units.
Data Sheet U14045EJ1V0DS00
31
PD780031AY, 780032AY, 780033AY, 780034AY
11. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand 1st Operand A #byte A
[HL + byte]
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
INC DEC
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP
[DE] [HL]
ROR4 ROL4
[HL + byte] [HL + B] [HL + C] X C
MOV
MULU DIVUW
Note
Except r = A
Data Sheet U14045EJ1V0DS00
32
PD780031AY, 780032AY, 780033AY, 780034AY
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW AX rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note
Only when rp = BC, DE or HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand 1st Operand A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY MOV1
$addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR
None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U14045EJ1V0DS00
33
PD780031AY, 780032AY, 780033AY, 780034AY
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVREF AVSS Input voltage VI1 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET P30 to P33 N-ch open-drain Without pull-up resistor With pull-up resistor Output voltage Analog input voltage VO VAN P10 to P17 Analog input pin Test Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3Note Unit V V V V V
-0.3 to VDD + 0.3Note -0.3 to +0.3 -0.3 to VDD + 0.3Note
VI2
-0.3 to +6.5 -0.3 to VDD + 0.3Note -0.3 to VDD + 0.3Note 0.3Note
V V V V
AVSS - 0.3 to AVREF + and -0.3 to VDD + 0.3Note -10 -15 -15 20 30 50 20 100 100 -40 to +85 -65 to +150
Output current, high
IOH
Per pin Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36
mA mA mA mA mA mA mA mA mA C C
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
Operating ambient temperature Storage temperature
TA Tstg
Note 6.5 V or below Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
34
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 P34 P50 P70 to to to to P03, P20 to P25, P36, P40 to P47, P57, P64 to P67, P75 MIN. TYP. MAX. 15 15 Unit pF pF
P30 to P33
20
pF
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = -40 to 85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
X1 X2 IC
Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH, tXL)
Test Conditions VDD = 4.0 to 5.5 V
MIN. 1.0 1.0
TYP.
MAX. 8.38 5.0 4
Unit MHz
C1
C2
After VDD reaches oscillation voltage range MIN. VDD = 4.0 to 5.5 V 1.0 1.0 VDD = 4.0 to 5.5 V
ms
Crystal resonator
X1
X2 IC
8.38 5.0 10 30
MHz
C1
C2
ms
External clock
VDD = 4.0 to 5.5 V
1.0 1.0
8.38 5.0 500 500
MHz
X1
X2
VDD = 4.0 to 5.5 V
50 85
ns
PD74HCU04
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
Data Sheet U14045EJ1V0DS00
35
PD780031AY, 780032AY, 780033AY, 780034AY
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL) VDD = 4.0 to 5.5 V Test Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz
XT2 R C4
XT1 IC
C3
1.2
2 10
s
External clock
32
38.5
kHz
XT2
XT1
PD74HCU04
5
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.
36
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Recommended Oscillator Constant Main system clock: Ceramic resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG040 CST2.00MG040 CSA3.58MG CST3.58MGW CSA4.19MG CST4.19MGW CSA5.00MG CST5.00MGW CSA8.00MTZ CST8.00MTW CSA8.00MTZ093 CST8.00MTW093 CSA8.38MTZ CST8.38MTW CSA8.38MTZ093 CST8.38MTW093 TDK CCR3.58MC3 CCR4.19MC3 CCR5.0MC3 CCR8.0MC5 CCR8.38MC5 1.00 2.00 2.00 3.58 3.58 4.19 4.19 5.00 5.00 8.00 8.00 8.00 8.00 8.38 8.38 8.38 8.38 3.58 4.19 5.00 8.00 8.38 Recommended Circuit Constant C1 (pF) 100 100 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip On-chip On-chip On-chip On-chip On-chip 100 100 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip On-chip On-chip On-chip On-chip On-chip C2 (pF) Oscillation Voltage Range MIN. (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 1.8 1.8 1.8 4.0 4.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use.
Data Sheet U14045EJ1V0DS00
37
PD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Output current, low Symbol IOH Per pin All pins IOL Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57 Input voltage, high VIH1 P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET P30 to P33 (N-ch open-drain) X1, X2 VDD = 2.7 to 5.5 V 0.7VDD 0.8VDD VDD = 2.7 to 5.5 V 0.8VDD 0.85VDD VDD = 2.7 to 5.5 V 0.7VDD 0.8VDD VDD = 2.7 to 5.5 V VDD - 0.5 VDD - 0.2 VIH5 XT1, XT2 VDD = 4.0 to 5.5 V 0.8VDD 0.9VDD Input voltage, low VIL1 P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET P30 to P33 VDD = 2.7 to 5.5 V 0 0 VDD = 2.7 to 5.5 V 0 0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V VIL4 X1, X2 VDD = 2.7 to 5.5 V 0 0 0 0 0 VIL5 XT1, XT2 VDD = 4.0 to 5.5 V 0 0 Output voltage, high Output voltage, low VOH1 VDD = 4.0 to 5.5 V, IOH = -1 mA IOH = -100 A VOL1 P30 to P33 P50 to P57 VDD = 4.0 to 5.5 V, IOL = 15 mA VDD - 1.0 VDD - 0.5 Test Conditions MIN. TYP. MAX. -1 -15 10 15 20 10 70 70 VDD VDD VDD VDD 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD VDD VDD 2.0 0.4 2.0 0.4 0.5 Unit mA mA mA mA mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V V
VIH2
VIH3
VIH4
VIL2
VIL3
P00 to P03, P20 to P25, P34 to P36, VDD = 4.0 to 5.5 V, P40 to P47, P64 to P67, P70 to P75 IOL = 1.6 mA VOL2 IOL = 400 A
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
38
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Test Conditions P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 VIN = 5.5 V VIN = 0 V P30 to P33Note P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 P30 to P33 VOUT = VDD VOUT = 0 V VIN = 0 V, P30, P31 VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75 15 15 30 30
Note
MIN.
TYP.
MAX. 3
Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 3 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Mask option pull-up resistance Software pullup resistance ILOH ILOL R1 R2
-20 -3 3 -3 90 90
A A A A
k k
Note Remark
When pull-up resistors are not connected to P30, P31 (specified by the mask option). Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14045EJ1V0DS00
39
PD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 1 Symbol IDD1 Test Conditions 8.38-MHz VDD = 5.0V10%Note 2 crystal oscillation operating mode When A/D converter is stopped When A/D converter is operating When A/D converter is stopped When A/D converter is operating VDD = 2.0V10%Note 3 When A/D converter is stopped When A/D converter is operating IDD2 8.38-MHz VDD = 5.0V10%Note 2 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating
IDD3
MIN.
TYP. 5.5 6.5 2 3 0.4 1.4 1.1
MAX. 11 13 4 6 1.5 4.2 2.2 4.7
Unit mA mA mA mA mA mA mA mA mA mA mA mA
5.00-MHz crystal oscillation operating mode
VDD = 3.0V10%Note 2
5.00-MHz VDD = 3.0V10%Note 2 crystal oscillation HALT mode
0.35
0.7 1.7
VDD = 2.0V10%Note 3
0.15
0.4 1.1
32.768-kHz crystal oscillation operating modeNote 4
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
40 20 10 30 6 2 0.1 0.05 0.05
80 40 20 60 18 10 30 10 10
A A A A A A A A A
IDD4
32.768-kHz crystal oscillation HALT modeNote 4
IDD5
XT1 = 0V STOP mode When feedback resistor is not used
Notes 1. Total current through the internal power supply (VDD0, VDD1), including the peripheral operation current (except the current through pull-up resistors of ports and the AVREF pin). 2. When the processor clock control register (PCC) is set to 00H. 3. When PCC is set to 02H. 4. When main system clock operation is stopped.
40
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
AC Characteristics (1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Operating with main system clock Test Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 0.24 0.4 1.6 Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/low -level width RESET low-level width tINTH, tINTL INTP0 to INTP3, P40 to P47 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tTIH0, tTIL0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 103.9Note 1 2/fsam + 0.1Note2 2/fsam + 0.2Note2 2/fsam + 0.5Note2 fTI5 VDD = 2.7 to 5.5 V 0 0 tTIH5, tTIL5 VDD = 2.7 to 5.5 V 100 1.8 1 2 tRSL 10 20 4 275 122 TYP. MAX. 16 16 16 125 Unit
s s s s s s s
MHz kHz ns ns
s s s s
Notes 1. Value when an external clock is used. When a crystal resonator is used, it is 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U14045EJ1V0DS00
41
PD780031AY, 780032AY, 780033AY, 780034AY
TCY vs. VDD (main system clock operation)
16.0 10.0
Cycle time TCY [ s]
5.0
Operation guaranteed range
2.0 1.6 1.0
0.4 0.24 0.1 0 1.0 1.8 2.0 2.7 3.0 4.0 5.0 5.5 6.0
Supply voltage VDD [V]
42
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = -40 to + 85C, VDD = 4.0 to 5.5 V) (1/3)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDADH 0.8tCY - 15 1.2tCY + 30 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 1.2tCY 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (2 + 2n)tCY 0 Test Conditions MIN. 0.3tCY 20 6 (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDWD tWRWD tWRADH tWTRD tWTWR
40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25
ns ns ns ns ns
Remarks
1. 2. 3.
tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U14045EJ1V0DS00
43
PD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = -40 to + 85C, VDD = 2.7 to 4.0 V) (2/3)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 1.2tCY 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (2 + 2n)tCY 0 Test Conditions MIN. 0.3tCY 30 10 (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 30
1.2tCY + 60
ns
Remarks
1. 2. 3.
tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
44
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = -40 to + 85C, VDD = 1.8 to 2.7 V) (3/3)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 40 0.8tCY - 60 0.5tCY 0.5tCY 240 1.2tCY + 120 2.5tCY + 100 2.5tCY + 100 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 20 (1.5 + 2n)tCY - 60 20 2tCY - 60 0.8tCY - 60 1.2tCY 0 (1.5 + 2n)tCY - 92 (2.5 + 2n)tCY - 92 tCY - 350 tCY - 132 tCY - 100 (2 + 2n)tCY 0 Test Conditions MIN. 0.3tCY 120 20 (2 + 2n)tCY - 233 (3 + 2n)tCY - 240 400 (2 + 2n)tCY - 325 (3 + 2n)tCY - 332 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 60
1.2tCY + 120
ns
Remarks
1. 2. 3.
tCY = TCY/4 n indicates the number of waits. CL = 100pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U14045EJ1V0DS00
45
PD780031AY, 780032AY, 780033AY, 780034AY
(3) Serial Interface (TA = -40 to + 85C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30 ... Internal clock output)
Parameter SCK30 cycle time Symbol tKCY1 Test Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 954 1600 3200 SCK30 high-/low-level width SI30 setup time (to SCK30) tSIK1 4.0 V VDD 5.5V 2.7 V VDD < 4.0V tKH1, tKL1 VDD = 4.0 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 SI30 hold time (from SCK30) SO30 output delay time from SCK30 tKSI1 C = 100 pFNote 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
tKSO1
300
ns
Note C is the load capacitance of the SCK30 and SO30 output lines. (b) 3-wire serial I/O mode (SCK30 ... External clock input)
Parameter SCK30 cycle time Symbol tKCY2 Test Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 800 1600 3200 SCK30 high-/low-level width tKH2, tKL2 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 400 800 1600 SI30 setup time (to SCK30) SI30 hold time (from SCK30) SO30 output delay time from SCK30 tSIK2 100 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSI2 C = 100 pFNote
400
ns
tKSO2
300
ns
Note C is the load capacitance of the SO30 output line.
46
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
(c) UART mode (Dedicated baud-rate generator output)
Parameter Transfer rate Symbol Test Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. TYP. MAX. 131031 78125 39063 Unit bps bps bps
(d) UART mode (External clock input)
Parameter ASCK0 cycle time Symbol tKCY3 Test Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 800 1600 3200 ASCK0 high-/low-level width tKH3, tKL3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 400 800 1600 Transfer rate 39063 19531 9766 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps
(e) UART mode (Infrared ray data transfer mode)
Parameter Transfer rate Bit rate allowable error Output pulse width Input pulse width Symbol Test Conditions VDD = 4.0 to 5.5 V VDD = 4.0 to 5.5 V VDD = 4.0 to 5.5 V VDD = 4.0 to 5.5 V 1.2 4/fX MIN. MAX. 131031 0.87 0.24/fbrNote Unit bps %
s
s
Note
fbr: Specified baud rate
Data Sheet U14045EJ1V0DS00
47
PD780031AY, 780032AY, 780033AY, 780034AY
(f) I2C bus Mode
Standard Mode Parameter SCL0 clock frequency Bus-free time (between stop and start condition) Hold timeNote 1 SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS compatible master I2C Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Spike pulse width controlled by input filter Capacitive load per bus line bus tSU:DAT tR tF tSU:STO tSP Cb Symbol MIN. fCLK tBUF 0 4.7 MAX. 100 -- MIN. 0 1.3 MAX. 400 -- kHz High-Speed Mode Unit
s s s s s s s
ns ns ns
tHD:STA tLOW tHIGH tSU:STA tHD:DAT
4.0 4.7 4.0 4.7 5.0 0Note 2 250 -- -- 4.0 -- --
-- -- -- -- -- -- -- 1000 300 -- -- 400
0.6 1.3 0.6 0.6 -- 0Note 2 100Note 4 20 + 0.1Cb 20 +
Note 5
-- -- -- -- -- 0.9Note 3 -- 300 300 -- 50 400
0.1CbNote 5 0.6 0 --
s
ns pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time. 2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal). 3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT needs to be fulfilled. 4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low state hold time tSU:DAT 250 ns * If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification). 5. Cb: Total capacitance per bus line (unit: pF)
48
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
AC Timing Test Points (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 Input
1/fXT
tXTL XT1 Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5 tTIL5 tTIH5
TI50, TI51
Data Sheet U14045EJ1V0DS00
49
PD780031AY, 780032AY, 780033AY, 780034AY
Read/Write Operation External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower-8-bit address tADS tASTH tADH
Hi-Z tRDAD tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower 8-bit address tADS tASTH tADH tRDAD
Hi-Z tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
50
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
External data access (no wait):
A8 to A15 tADD2 AD0 to AD7 Lower 8-bit address tADS tASTH ASTB tADH Hi-Z tRDAD tRDD2
Higher 8-bit address
Read data
Write data
Hi-Z
tRDH
RD tASTRD WR tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15 tADD2 AD0 to AD7
Lower 8-bit address
Higher 8-bit address Hi-Z tRDAD tRDH tRDD2 tASTRD Hi-Z
Read data
Write data
tADS tADH tASTH ASTB
RD tRDL2 WR tASTWR WAIT tRDWT2 tWTL tWTRD
tRDWD tWRWD
tWDS
tWDH
tWRL1
tWRADH
tWTL tWRWT tWTWR
Data Sheet U14045EJ1V0DS00
51
PD780031AY, 780032AY, 780033AY, 780034AY
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK30 tSIKm tKSIm
SI30 tKSOm
Input data
SO30 m = 1, 2
Output data
UART mode (external clock input):
tKCY3 t KL3 tKH3
ASCK0
52
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
I2C Bus Mode:
tLOW tR SCL0 tHD:DAT tHD:STA tF
tHIGH tSU:DAT
tSU:STA
tHD:STA
tSP
tSU:STO
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U14045EJ1V0DS00
53
PD780031AY, 780032AY, 780033AY, 780034AY
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Conversion time tCONV 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Zero-scale offsetNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Full-scale offsetNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Integral linearity errorNote 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Differential linearity errorNote 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Analog input voltage Reference voltage Resistance between AVREF and AVSS VIAN AVREF RREF When A/D conversion is not performed 0 1.8 20 40 14 19 28 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 0.6 MAX. 10 0.4 0.6 1.2 96 96 96 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5 AVREF AVDD Unit bit %FSR %FSR %FSR
s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V V k
Notes 1. Excludes quantization error (1/2 LSB). 2. Shown as a percentage of the full scale value.
54
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization time tSREL tWAIT Release by RESET Release by interrupt request Symbol VDDDR Test Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.6 V Subsystem clock stop (XT1 = VDD) and feed-back resistor disconnected 0
0.1
30
A
s
217/fx Note ms ms
Note Selection of
212/fX
and
214/fX
to
217/fX
is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS). Data Retention Timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Sheet U14045EJ1V0DS00
55
PD780031AY, 780032AY, 780033AY, 780034AY
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP Instruction execution Standby release signal (interrupt request)
VDDDR tSREL
tWAIT
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
56
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
13. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K J I L
H G
NOTES
F D
C N
M
B
M
R
ITEM
MILLIMETERS 58.0+0.68 -0.20 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.05+0.26 -0.20 5.08 MAX. 19.05 (T.P.) 17.00.2 0.25+0.10 -0.05 0.17 0 to 15
INCHES 2.283+0.028 -0.008 0.070 MAX. 0.070 (T.P.) 0.020+0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.159+0.011 -0.008 0.200 MAX. 0.750 (T.P.) 0.669+0.009 -0.008 0.010+0.004 -0.003 0.007 0 to 15 P64C-70-750A,C-3
1. Controlling dimension
millimeter.
A B C D F G H I J K L M N R
2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel.
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
Data Sheet U14045EJ1V0DS00
57
PD780031AY, 780032AY, 780033AY, 780034AY
64 PIN PLASTIC QFP ( 14)
A B
48 49
33 32
detail of lead end S CD Q R
64 1
17 16
F G H P I
M
J
K S
N
NOTE 1. Controlling dimension
S
L M
ITEM MILLIMETERS 17.60.4 14.00.2 14.00.2 17.60.4 1.0 1.0 0.37 +0.08 -0.07 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.17 +0.08 -0.07 0.10 2.550.1 0.10.1 55 2.85 MAX. INCHES 0.6930.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.039 0.039 0.015 +0.003 -0.004 0.006 0.031 (T.P.) 0.0710.008 0.031 +0.009 -0.008 0.007 +0.003 -0.004 0.004 0.1000.004 0.0040.004 55 0.113 MAX. P64GC-80-AB8-4
millimeter.
A B C D F G H I J K L M N P Q R S
2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
58
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
64 PIN PLASTIC LQFP (12x12)
A B
48 49
33 32 detail of lead end S
C
D R Q
64 1 F
17 16
G H I
M
J
P
K S L M
ITEM A B C D F G
MILLIMETERS 14.80.4 12.00.2 12.00.2 14.80.4 1.125 1.125 0.320.08 0.13 0.65 (T.P.) 1.40.2 0.60.2 0.17 +0.08 -0.07 0.10 1.40.1 0.1250.075 55 1.7 MAX.
INCHES 0.5830.016 0.472+0.009 -0.008 0.472+0.009 -0.008 0.5830.016 0.044 0.044 0.013+0.003 -0.004 0.005 0.026 0.0550.008 0.024+0.008 -0.009 0.007+0.003 -0.004 0.004 0.055+0.004 -0.005 0.0050.003 55 0.067 MAX. P64GK-65-8A8-2
N
S
NOTES 1. Controlling dimension millimeter.
H I J K L M N P Q R S
2. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
Data Sheet U14045EJ1V0DS00
59
PD780031AY, 780032AY, 780033AY, 780034AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 14-1. Surface Mounting Type Soldering Conditions (1) PD780031AYGC-xxx-AB8: 64-pin plastic QFP (14 x 14 mm)
PD780032AYGC-xxx-AB8: 64-pin plastic QFP (14 x 14 mm) PD780033AYGC-xxx-AB8: 64-pin plastic QFP (14 x 14 mm) PD780034AYGC-xxx-AB8: 64-pin plastic QFP (14 x 14 mm)
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow VPS Wave soldering
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Partial heating
--
Caution Do not use different soldering methods together (except for partial heating).
60
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
(2) PD780031AYGK-xxx-8A8: 64-pin plastic LQFP (12 x 12 mm)
PD780032AYGK-xxx-8A8: 64-pin plastic LQFP (12 x 12 mm) PD780033AYGK-xxx-8A8: 64-pin plastic LQFP (12 x 12 mm) PD780034AYGK-xxx-8A8: 64-pin plastic LQFP (12 x 12 mm)
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: two times or less, Exposure limit: 7 days Note (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
--
Note After opening the dry pack, store it at 25C or less and 65%RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
Table 14-2. Insertion Type Soldering Conditions
PD780031AYCW-xxx: 64-pin plastic shrink DIP (750mils) PD780032AYCW-xxx: 64-pin plastic shrink DIP (750mils) PD780033AYCW-xxx: 64-pin plastic shrink DIP (750mils) PD780034AYCW-xxx: 64-pin plastic shrink DIP (750mils)
Soldering Method Wave soldering (only for pins) Partial heating Soldering Conditions Solder bath temperature: 260C max., Time: 10 seconds max. Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
Data Sheet U14045EJ1V0DS00
61
PD780031AY, 780032AY, 780033AY, 780034AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780034AY Subseries. Also refer to (5) Cautions on Using Development Tools. (1) Language Processing Software
RA78K/0 CC78K/0 DF780034 CC78K/0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file common to PD780034A Subseries C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (FL-PR2) Flashpro III (FL-PR3, PG-FP3) FA-64CW FA-64GC FA-64GK Flash programmer dedicated to microcontrollers with on-chip flash memory
Adapter for flash memory writing
(3) Debugging Tools * When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PANote IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-780034-NS-EM1 NP-64CW NP-64GC NP-64GC-TQ NP-64GK TGK-064SBW In-circuit emulator common to 78K/0 Series Power supply unit for IE-78K0-NS Performance board to enhance and expand the functions of IE-78K0-NS Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported) Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is embedded as host machine Emulation board to emulate PD780034AY Subseries Emulation probe for 64-pin plastic shrink DIP (CW type) Emulation probe for 64-pin plastic QFP (GC-AB8 type)
Emulation probe for 64-pin plastic LQFP (GK-8A8 type) Conversion adapter to connect NP-64GK and target system board on which a 64-pin plastic LQFP (GK-8A8 type) can be mounted. Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type) Integrated debugger for IE-78K0-NS System simulator common to 78K/0 Series Device file common to PD780034A Subseries
EV-9200GC-64 ID78K0-NS SM78K0 DF780034
Note
Under development
62
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
* When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-780034-NS-EM1 IE-78K0-R-EX1 EP-78240CW-R EP-78240GC-R EP-78012GK-R TGK-064SBW In-circuit emulator common to 78K/0 Series Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is embedded as host machine Interface adapter and cable when using EWS as host machine Emulation board to emulate PD780034AY Subseries Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A Emulation probe for 64-pin plastic shrink DIP (CW type) Emulation probe for 64-pin plastic QFP (GC-AB8 type) Emulation probe for 64-pin plastic LQFP (GK-8A8 type) Conversion adapter to connect EP-78012GK-R and target system board on which a 64-pin plastic LQFP (GK-8A8 type) can be mounted. Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type) Integrated debugger for IE-78001-R-A System simulator common to 78K/0 Series Device file common to PD780034A Subseries
EV-9200GC-64 ID78K0 SM78K0 DF780034
(4) Real-time OS
RX78K/0 MX78K0 Real-time OS for 78K/0 Series OS for 78K/0 Series
Data Sheet U14045EJ1V0DS00
63
PD780031AY, 780032AY, 780033AY, 780034AY
(5) Cautions on Using Development Tools * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034. * The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034. * FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK, NP-64CW, NP-64GC, NP-64GC-TQ, and NP-64GK are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. * The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) * For third-party development tools, see the 78K/0 Series Selection Guide (U11126E). * The host machines and OSs supporting each software are as follows.
Host Machine [OS] Software RA78K/0 CC78K/0 ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0
PC PC-9800 series [WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] - -
Note
Note
Note
DOS-based software
64
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No. (English) U14046E This document U14041E U12326E -- -- Document No. (Japanese) U14046J U14045J U14041J U12326J U10903J U10904J
PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual PD780031AY, 780032AY, 780033AY, 780034AY Data Sheet PD78F0034AY Data Sheet
78K/0 Series User's Manual Instructions 78K/0 Series Instruction Table 78K/0 Series Instruction Set
Documents Related to Development Tools (User's Manuals)
Document Name Document No. (English) Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language CC78K0 C Compiler Application Note IE-78K0-NS IE-78001-R-A IE-780034-NS-EM1 EP-78240 EP-78012GK-R SM78K0 System Simulator Windows based SM78K Series System Simulator Reference External Part User Open Interface Specifications Programming Know-how U11802E U11801E U11789E EEU-1402 U11517E U11518E U13034E To be prepared To be prepared To be prepared U10332E EEU-1538 U10181E U10092E Document No. (Japanese) U11802J U11801J U11789J U12323J U11517J U11518J U13034J To be prepared To be prepared To be prepared EEU-986 EEU-5012 U10181J U10092J
RA78K0 Assembler Package
ID78K0-NS Integrated Debugger Windows based Reference ID78K0 Integrated Debugger EWS based ID78K0 Integrated Debugger PC based ID78K0 Integrated Debugger Windows based Reference Reference Guide
U12900E -- U11539E U11649E
U12900J U11151J U11539J U11649J
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14045EJ1V0DS00
65
PD780031AY, 780032AY, 780033AY, 780034AY
Documents Related to Embedded Software (User's Manuals)
Document Name Document No. (English) Basics Installation 78K/0 Series OS MX78K0 Basics U11537E U11536E U12257E Document No. (Japanese) U11537J U11536J U12257J
78K/0 Series Real-time OS
Other Related Documents
Document Name Document No. (English) X13769X C10535E C11531E C10983E C11892E -- C10535J C11531J C10983J C11892J U11416J Document No. (Japanese)
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
66
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
[MEMO]
Data Sheet U14045EJ1V0DS00
67
PD780031AY, 780032AY, 780033AY, 780034AY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
68
Data Sheet U14045EJ1V0DS00
PD780031AY, 780032AY, 780033AY, 780034AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14045EJ1V0DS00
69
PD780031AY, 780032AY, 780033AY, 780034AY
FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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